This invention relates to Flash Electrically-Programmable Erasable Read-Only-Memories (Flash EPROMs). In particular, this invention relates to a circuit for protecting such devices from stress, or soft program, during either program or erase operation.
Flash EPROMs are generally described in U.S. patent application Ser. No. 08/315,526 filed Sep. 30, 1994, entitled "FLASH EPROM CONTROL WITH EMBEDDED PULSE TIMER AND WITH BUILT-IN SIGNATURE ANALYSIS", also assigned to Texas Instruments Incorporated. That Patent Application is hereby incorporated herein.
The memory cell arrays of many Flash EPROMs are formed in groups of rows and columns of memory cells, or sectors of memory cells. In many such cases, the various sectors share wordlines (connected to control gates of memory cells) and/or bitlines (connected to the drains of memory cells) with other sectors. In the type of memory-cell array discussed here, the sources of all of the memory cells in a sector are connected to a common terminal, called an "array-source line".
In Flash EPROMs that do not have electrically isolated sectors or have sectors with weak electrical isolation, a program or erase operation in one sector may disturb (stress, or soft program) the other sectors. The degree of damage to other sectors increases with the number of program or erase cycles that cause voltage stress on those other sectors.
There is a need for a sequence of applying voltages to array-source lines, bitlines and wordlines of sectors during operations such that the sequence reduces disturb voltages in other sectors. Fulfillment of that need would improve the endurance of Flash EPROM devices.
Past methods for solving the problem have involved applying a low voltage at the array-source line terminal to improve the endurance.